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Three (3) IPC-B-24 test patterns.
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No mask ((laminate/flux interactions) to
correlate with J-STD-004 SIR tests.
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Striped mask (solder mask developing
check and entrapment effects).
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Full mask (effect of flux on solder mask
properties).
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A row of 0805 chips (1.0 meg ohm, 0.1
watt) – used for checking for electromigration under caps and
adhesive characteristics.
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A row of 1206 chips – same.
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Three (3) header patterns – used to study
paste qualities, effects of peelable latex mask, or touch-up
soldering operations.
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One (1) BGA test pattern using an
isolated die (tests for residues under BGAs).
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One (1) QFP test pattern using an
isolated die (residues under QFPs).
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One LCC test pattern (tests for low stand
off cleaning challenges) – identical to IPC-B-36 quadrant D
patterns.
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One (1) row of DIPs for through hole
processes (checks for fillet formation).
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One (1) PGA socket – used to examine
entrapment effects of sockets.
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A snap-off coupon containing a Bellcore
pattern with crosshatched mask – used to test SIR per Bellcore
CR-78-CORE for telecommunications assemblers.
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A snap-off coupon containing an IPC-B-36
Quadrant D pattern – used for military and IPC Class 3
customers for J-STD-001 qualification.